1. Field of the Invention
This invention is directed to logic design. More particularly, this invention is directed to correcting timing problems encountered when rules for a given technology are assigned to a technology-independent logic model.
2. Discussion of Related Art
Automation of the mapping and optimization of logic data arrays for a given technology can provide savings in design time and significant improvement in the performance of the circuits produced. The possibility of automating the translation of a functional specification into its hardware implementation has long been the subject of investigation. The complexity of this task and the potential value of its automation have continued to grow with the increasing complexity of the devices being designed and the mounting pressure to shorten machine design times.
Early attempts at automated logic synthesis concentrated on deriving a minimized Boolean expression for reducing the number of gates in the functional specification. More recent efforts have provided technology-specific designs and, as the technologies become increasingly sophisticated, synthesis systems are compelled to deal with a growing number of technology-specific criteria in order to achieve acceptable implementation. Gate count continues to be a major factor in design acceptability but timing constraints and the efficient use of primitives available in the particular technology are increasingly important.
The logic synthesis procedure for implementing a model in a given technology generally begins by performing logic reduction transformations on a technology-independent model, such as the Boolean transformations mentioned earlier. Subsequent transformations, to implement timing criteria and other technology-specific features required of the model, are then performed on a technology-legal model, after mapping the technology onto the model.
Timing can be optimized by analyzing path delays, as disclosed in U.S. Pat. No. 4,263,651 issued Apr. 21, 1981 to Donath et al. and commonly assigned. However, this analysis calculates timing data for the entire model. Once any timing corrections have been made, the timing data thus calculated is not up to date. Any further timing corrections may be erroneous unless the timing data for the model is recalculated. However, the size of the logic arrays required in the present state of technology has grown to a point where this kind of brute force recalculation imposes a severe penalty on the efficiency of the design process.
A logic synthesis method which maximizes the use of primitives specific to the technology in order to minimize gate count is disclosed in U.S. Pat. No. 4,703,435, issued Oct. 7, 1987 to Darringer et al. and commonly assigned. This known method reduces the number of logic blocks in a technology-independent model, limits fan-in, and maximizes the use of negative logic NAND and NOR gates in that model before mapping the given technology to the model. This preliminary model can be modified to maximize either size or speed before the technology is mapped to it, but timing constraints are not implemented until after a technology-legal "hardware" model has been defined.
However some transformations cannot be used to correct the initial allocation of the technology to the blocks of the model. Permitting these transforms to produce violations of the technology rules at this late stage, in an otherwise technology-legal model, would disrupt the logic synthesis process. Thus the hardware model produced by this method may be unable to satisfy the required timing constraints, requiring a repeat of the logic synthesis process before achieving the required hardware implementation of a technology-independent model. Furthermore, this method provides less control over the size of the resulting technology-legal model, producing cell counts that are apt to be about 30% higher than those produced in accordance with the present invention.
A method of optimizing timing by allocating selectable power levels within a given device allocation is disclosed in U.S. Pat. No. 4,698,760 issued Oct. 6, 1987 to Lembach et al. and commonly assigned. However, this method cannot exploit the advantages that may be available if higher-powered devices are substituted for the devices assigned by the initial device allocation. Instead, it relies on the variability of the power/performance characteristics of the devices themselves.